1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a semiconductor memory device including a power supply voltage generation circuit shared by banks.
2. Description of the Background Art
An external power supply potential ext.Vdd supplied to a semiconductor chip is increasingly reduced in response to requirement for low power consumption in a system using the semiconductor chip, for example. In practice, however, it is problematic to employ the reduced external power supply potential ext.Vdd as an operating power supply potential for a transistor provided in the semiconductor chip as such, in consideration of reliability. Therefore, an internal power supply potential Vdd lower than the external power supply potential ext.Vdd is generally generated in the chip and used as the operating power supply potential for the transistor.
FIG. 18 is a block diagram showing the structure of a synchronous dynamic random access memory (SDRAM 501) as an exemplary conventional semiconductor chip.
Referring to FIG. 18, the SDRAM 501 includes four banks 0 to 3, having a storage capacity of 256 megabits in total, capable of operating independently of each other. The SDRAM 501 performs read/write operations in synchronization with an externally supplied clock signal CLK. In order to perform a desired operation, a command decided by a combination of control signals /RAS, /CAS and /WE is supplied. A control signal /CS instructing selection of any chip, a control signal CKE instructing whether or not to capture the clock signal CLK and the like are also properly supplied from an external device.
The SDRAM 501 further includes a power supply potential generation circuit 510 receiving and stepping down an external power supply potential ext.Vdd for outputting an internal power supply potential Vdd. The power supply potential generation circuit 510 indudes a VDC control circuit 532 receiving a row activation signal from each of row decoders & word drivers 10#0 to 10#3 provided in correspondence to memory array banks 14#0 to 14#3 respectively and outputting a signal PWRUP, a Vref generation circuit 534 generating a reference potential Vref, and a VDC (voltage down convertor) 536 receiving the reference potential Vref and stepping down the external power supply potential ext.Vdd to the same level as the reference potential Vref at a response speed responsive to the signal PWRUP for outputting the power supply potential Vdd.
FIG. 19 is an operation waveform diagram showing waveforms of external signals in a write operation of the SDRAM 501.
Referring to FIG. 19, the waveforms show operations with reference to a RAS-CAS delay time tRCD and a row precharge time tRP of three cycles and a burst length BL of 4.
At a time t1, a command ACT[0] for activating a row system of the bank 0 is input on the leading edge of the clock signal CLK. Each command is input with a bank address denoted by a bracketed numeral.
At the same time, a row address X for selecting a single word line WL is supplied as a combination of signals A0 to A12 and the bank address designating the bank 0 is supplied as a combination of signals BA0 and BA1.
On the leading edge of the clock signal CLK at a time t4 after three cycles, a command WRITE[0] for performing a write operation on the already activated word line WL is input. At the same time, a column address Y is supplied as a combination of the signals A0 to A9, and the bank address is also supplied. The command WRITE is decided by a combination of control signals ICS, /RAS, /CAS and /WE. In four cycles from the time t4 to a time t7, write data D0 to D3 are externally supplied by a combination of signals DQ0 to DQ15 and written in a memory cell.
At a time t8, a command PRE[0] for resetting the word line WL of the active bank 0 is input. The command PRE is supplied by a combination of he control signals /CS, /RAS, /CAS and /WE. After the final data D3 is written, a time tWR must be set before the command PRE[0] is input, in order to guarantee that the data are reliably written in the memory cell. Data can be written in a specific bank in the aforementioned manner.
When continuously accessing the same bank 0, a time exceeding a row precharge time tRP must be set before inputting the next command ACT[0].
A representative specification of such an SDRAM is referred to as "PC 100", and the following description is made with reference to the SDRAM 501 based on PC 100.
When performing the operations shown in FIG. 19, current consumption in the SDRAM 501 temporally changes under the internal power supply potential Vdd.
FIG. 20 is a schematic waveform diagram showing temporal change of current consumption.
Referring to FIG. 20, current consumption starting from each command input abruptly increases under the power supply potential Vdd in a single row cycle, i.e., a cycle for executing the commands ACT, WRITE and PRE. The SDRAM 501 performing a read/write operation at a high speed exhibits extremely large peak and average values of current consumption. On the other hand, the SDRAM 501 exhibits small current consumption in periods between the times t2 and t3 and between the times t4 and t5, i.e., periods Trs1 and Trs2 after completing prescribed operations and before receiving next commands. In general, the period Trs1 or Trs2 is referred to as an active standby period, which is different from the so-called standby period when no row system is activated. A current Ias consumed in the active standby state is larger than a current Iss consumed in the standby state due to activation of the row system. In order to cope with such fluctuation of current consumption under the power supply potential Vdd, the VDC (voltage down convertor) 536 generating the power supply potential Vdd must be properly controlled.
The VDC 536 shown in FIG. 18 is formed by a comparator and a driver, as described later with reference to embodiments of the present invention. The operating speed of the comparator increases in response to a through current Ic flowing therein, while this through current Ic is preferably reduced in the standby period or the active standby period. Therefore, the VDC control circuit 532 changes the signal PWRUP output therefrom in response to a current consumed in a power source for switching the value of the through current Ic.
FIG. 21 is a diagram for illustrating the structure of the VDC control circuit 532 shown in FIG. 18.
Referring to FIGS. 18 and 21, a control circuit & mode register 8 shown in FIG. 18 includes a bank address decoder 92, a command decoder 94 and a selection circuit 96. The bank address decoder 92 receives internal bank address signals int.BA0 and int.BA1 from an address buffer 2, decodes the same and outputs bank designation signals BAD0 to BAD3. Each prefix "int." indicates that the signal is obtained by latching an externally supplied signal in a high-level period of an internal clock signal CLKI.
The command decoder 94 receives control signals int.RAS, int.CAS and int.WE from a control signal input buffer 6, decodes the same and outputs a signal ACTF indicating input of an ACT command and a signal PREF indicating input of a PRE command. The signals ACTF and PREF are generated irrelevantly to bank information. The selection circuit 96 receives the bank designation signals BAD0 to BAD3 and the signals ACTF and PREF. The selection circuit 96 generates signals ACTF0 to ACTF3 activating row systems of the banks 0 to 3 and signals PCGF0 to PCGF3 inactivating the row systems of the banks 0 to 3. These signals ACTF0 to ACTF3 and PCGF0 to PCGF3 go high only by one cycle in the designated banks 0 to 3.
These signals ACTF0 to ACTF3 and PCGF0 to PCGF3 are input in latches 100#0 to 100#3 provided in correspondence to the banks 0 to 3 respectively. The latches 100#0 to 100#3 are included in the row decoders & word drivers 10#0 to 10#3 provided in an area 98 arranged in proximity to the banks 0 to 3 respectively.
For simplifying illustration, FIG. 21 shows the area 98 as a single one. In practice, however, such an area 98 is arranged in a position separated from a peripheral area provided with the selection circuit 96 etc., i.e., in proximity to each of the banks 0 to 3, and not collectively arranged.
The VDC control circuit 532 includes a four-input NAND circuit 542 receiving signals ZRASE0 to ZRASE3 held by the latches 100#0 to 100#3 respectively for indicating activation of the banks 0 to 3, a delay circuit 544 delaying and outputting an output of the NAND circuit 542, a NOR circuit 546 receiving the outputs of the NAND circuit 542 and the delay circuit 544 and an invertor 548 receiving and inverting an output of the NOR circuit 546 and outputting the signal PWRUP.
FIG. 22 is a circuit diagram showing the structure of the selection circuit 96 appealing in FIG. 21.
Referring to FIG. 22, the selection circuit 96 includes a gate circuit 552 provided in correspondence to the bank 0, a gate circuit 554 provided in correspondence to the bank 1, a gate circuit 556 provided in correspondence to the bank 2, and a gate circuit 558 provided in correspondence to the bank 3.
The gate circuit 552 includes a NAND circuit 562 receiving the bank designation signal BAD0 and the signal ACTF, an invertor 564 receiving and inverting an output of the NAND circuit 562 and outputting the signal ACTF0, an OR circuit 566 receiving the bank designation signal BAD0 and an internal address signal int.A10, a NAND circuit 568 receiving an output of the OR circuit 566 and the signal PREF, and an invertor 570 receiving and inverting an output of the NAND circuit 568 and outputting the signal PCGF0.
The gate circuit 554 receives the bank designation signal BAD1 in place of the bank designation signal BAD0 and outputs the signals ACTF1 and PCGF1 in place of the signals ACTF0 and PCGF0 in the circuit structure of the gate circuit 552. The gate circuit 556 receives the bank designation signal BAD2 in place of the bank designation signal BAD0 and outputs the signals ACTF2 and PCGF2 in place of the signals ACTF0 and PCGF0 in the circuit structure of the gate circuit 552. The gate circuit 558 receives the bank designation signal BAD3 in place of the bank designation signal BAD0 and outputs the signals ACTF3 and PCGF3 in place of the signals ACTF0 and PCGF0 in the circuit structure of the gate circuit 552. Therefore, description of these gate circuits 554, 556 and 558 is not particularly repeated.
The row systems of all banks 0 to 3 are reset when the address signal A10 is high in a PRE command on the specification of the SDRAM 501, and hence the signals PCGF0 to PCGF3 for resetting the row systems of the banks 0 to 3 simultaneously go high when the signal int.A10 goes high in the selection circuit 96.
Referring again to FIG. 21, the signals ACTF0 to ACTF3 and PCGF0 to PCGF3 having bank information are transmitted to the corresponding banks 0 to 3 and input in the latches 100#0 to 100#3. When the signals ACTF0 to ACTF3 go high, the latches 100#0 to 100#3 set the signals ZRASE0 to ZRASE3 indicating activation of the row systems low. The signals ZRASE0 to ZRASE3 go low when the row systems are activated. The latches 100#0 to 100#3 are reset when the signals PCGF0 to PCGF3 go high. In other words, the signals ZRASE0 to ZRASE3 go high at this time.
The VDC 536 shown in FIG. 18 increases the through current Ic in the internal comparator when the row system is activated in any of the banks 0 to 3 to cope with increase of current consumption, and hence the signal PWRUP instructing this operation is activated when any of the signals ZRASE0 to ZRASE3 is low. As shown in FIG. 21, generation of the signal PWRUP can be implemented by NANDing the signals ZRASE0 to ZRASE3 indicating activation of the four banks 0 to 3. The delay stage for delaying fall of the signal PWRUP from a high level to a low level is provided in order to compensate for increase of current consumption when the row systems are reset. When a PRE command is received, the latches 100#0 to 100#3 shown in FIG. 21 are reset and the signals ZRASE0 to ZRASE3 indicating activation of the banks 0 to 3 return to high levels. Therefore, the delay stage is provided for compensating for a power supply current consumed when the row systems are reset between the times t5 to tG shown in FIG. 20.
FIG. 23 is a waveform diagram for illustrating the signal PWRUP. Referring to FIGS. 21 and 23, the signal ZRASE0 for the bank 0 goes low when the command ACT[0] is input at the time t1, and hence the signal PWRUP responsively goes high. The signal PWRUP remains high up to the time t5 when the command PRE[0] input. When the command PRE[0] is input at the time t5, the latch 100#0 is responsively reset and the signal ZRASE0 goes high. Then, the signal PWRUP falls to a low level at the time t6 after a lapse of a delay time Td11 of the delay circuit 544.
FIG. 24 is a waveform diagram for studying a waveform of the signal PWRUP for controlling the through current Ic of the comparator with more fidelity to increase/decrease of current consumption.
Referring to FIG. 24, consumption of the power supply current peaks for a constant time after input of a command, and thereafter enters an active standby state or a standby state. Therefore, there may be provided a circuit setting the signal PWRUP high for a delay time Td21 corresponding to the times t1 to t2 when the command ACT[0] is input, keeping the same high for a delay time Td22 corresponding to the times t3 to t4 when the command WRITE[0] is input and keeping the same high for a delay time Td23 corresponding to the times t5 to t6 when the command PRE[0] is input.
In order to simplify the description, study is made only on a part setting the signal PWRUP high for a constant period starting from an ACT command. It is to be noted that a multi-bank structure is allowed to activate a plurality of banks one after another and the signal PWRUP must necessarily be high during a row-system activation period of any activated bank.
FIG. 25 is a circuit diagram showing the structure of a circuit 590 controlling activation of the signal PWRUP corresponding to the ACT command.
Referring to FIG. 25, the circuit 590 includes a pulse generation circuit 592 outputting a pulse signal REP0 of a constant width in response to activation of the signal ZRASE0 shown in FIG. 21, a pulse generation circuit 594 outputting a pulse signal REP1 in response to activation of the signal ZRASE1, a pulse generation circuit 596 outputting a pulse signal REP2 in response to activation of the signal ZRASE2, a pulse generation circuit 598 generating a pulse signal REP3 in response to activation of the signal ZRASE3, a four-input NOR circuit 600 receiving the pulse signals REP0 to REP3 and an invertor 602 receiving and inverting an output of the NOR circuit 600. The invertor 602 outputs the signal PWRUP.
The pulse generation circuit 592 includes a delay circuit 604 receiving the signal ZRASE0 and delaying the same by the delay time Td21, an invertor 606 receiving and inverting an output of the delay circuit 604, and a NOR circuit 608 receiving the signal ZRASE0 and an output of the invertor 606 and outputting the pulse signal REP0.
The pulse generation circuits 594 to 598 receive the signals ZRASE1 to ZRASE3 in inputs thereof and output the signals REP1 to REP3 respectively. These pulse generation circuits 594 to 598 are similar in structure to the pulse generation circuit 592, and hence redundant description is not repeated.
FIG. 26 is an operation waveform diagram showing waveforms appearing when commands ACT[0] to ACT[3] are continuously input in the circuit 590 shown in FIG. 25.
When the command ACT[0] is input at a time t1, the signal ZRASE0 indicating activation of the bank 0 is activated low. The pulse generation circuit 592 responsively sets the pulse signal REP0 high for the delay time Td21. The delay time Td21 is set to correspond to a current increase period by the ACT command shown in FIG. 24. Similarly, the commands ACT[1], ACT[2] and ACT[3] are input at times t2, t3 and t4 respectively for activating the pulse signals REP1 to REP3 for the delay time Td21 respectively. The signal PWRUP has a continuous waveform due to such a circuit structure. In other words, the voltage down convertor (VDC) 536 can cope with increase of current consumption following continuous activation of a plurality of banks.
While the above description is made with reference to extremely simplified control of the through current Ic, the through current Ic can be more strictly controlled with a plurality of control signals.
When commands are temporally discretely supplied for a plurality of banks, a time lag results in change of the current consumed in each bank. It is important in control of a voltage down convertor (VDC) shared by banks in a multi-bank structure that the voltage down convertor can cope with this time lag with a sufficient response speed and sufficient drivability.
In the exemplary circuits shown in FIGS. 21 and 25, the signals including bank information or the derivative signals generated on the basis thereof are unified to decide the period for activating the signal PWRUP high. If the number of banks is increased, however, the number of signals for generating the signal PWRUP is extremely increased.
In the circuit structure shown in FIG. 21, the signals ZRASE0 to ZRASE3 are generated in portions close to the respective banks 0 to 3 and hence these signals ZRASE0 to ZRASE3 must be temporarily collected in order to generate the signal PWRUP.
As described above, the selection circuit 96 is generally arranged on a space between the banks 0 to 3 where peripheral circuits are arranged. The VDC control circuit 532 is arranged in proximity to the voltage down convertor 536 in a space between the banks 0 to 3 similarly to the selection circuit 96. The latches 100#0 to 100#3 arranged in proximity to the banks 0 to 3 are located on positions separate from the VDC control circuit 532. In other words, long wires must be provided between the latches 100#0 to 100#3 and the VDC control circuit 532.
These wires must be provided on wiring areas of narrow spaces between the banks 0 to 3 over long distances, disadvantageously resulting in increase of the chip area. While the VDC control circuit 532 may have latches identical to those provided for the banks 0 to 3, the circuit scale is disadvantageously increased if the number of banks is increased. In the circuit structure shown in FIG. 25, delay stages must be provided for the signals ZRASE0 to ZRASE3 respectively, to disadvantageously complicate the circuit structure and also result in increase of the layout area. Thus, when the voltage down convertor (VDC) 536 shared by the banks 0 to 3 is controlled with the signals including bank information, waste of circuits and wires is increased as the number of banks is increased.